Transistor density varies for different chip structures. Meanwhile, Apple A14 Bionic’s transistor density seems somewhat lower than TSMC’s theoretical peak average transistor density promised for N5-based SoCs. Considering that semiconductor makers tend to use different methodologies when measuring transistor density, we cannot really compare TSMC’s N5 to Intel’s 10 nm’s ~ 100 mega transistors per mm2, as that would be an apples-to-oranges kind of comparison. The average transistor density of the A14 Bionic chip is 134.09 million transistors per mm2, up from 89.97 million transistors per mm2 in the case of the A13 Bionic, according to SemiAnalyis. We know that Apple has used a unified system cache in recent years, but it is not easy to find it on the image. The quality of the image is not exactly high, but with rough napkin math, we can gather that the dual-core FireStorm complex with a big L2 cache is around 9.1 mm2, the quad-core IceStorm complex with a small L2 cache is approximately 6.44mm2, and the GPU occupies about 11.65mm2. The A14 Bionic processor has a die size of 88mm2, down from 98.48mm2 in the case of the A13 Bionic. A quad-cluster GPU, a 16-core neural engine with 11 TOPS of performance, and a variety of special-purpose accelerators complete the SoC. The chip packs six general-purpose processing cores consisting of two high-performance FireStorm cores and four IceStorm cores. But can a die shot of Apple’s A14 give any idea about what to expect from the company’s upcoming processors for notebooks and desktops? Apple’s A14 Bionic: A 88mm2 Power HouseĪpple’s A14 Bionic SoC consists of 11.8 billion transistors and is made using TSMC’s N5 (5nm) process technology. Such details expose the capabilities of process technologies and some aspects of the priorities of chip designers. An insightful report written by Sem iAnalysis revealed die size and transistor density of the SoC. ICmasters, a semiconductor reverse engineering and IP services company, has done a preliminary examination of Apple’s A14 Bionic system-on-chip (SoC) using a transmission electron microscopy (TEM).
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